(VRV32A Load-Reserved/Store-Conditional Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I2
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I8
sVwid_order
p12
I8
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_LR.W
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I4
sg8
g17
sVtag
p23
VVP_IP008_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F008_S000_I000
p34
sVdescription
p35
Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 8.2
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_ISA_F008_S000_I001
p62
sg35
Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception
p63
sg37
VUnprivileged ISA\u000aChapter 8.2
p64
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled
p65
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
a(V002
p71
g1
(g29
g3
Ntp72
Rp73
(dp74
g8
V002
p75
sg23
VVP_ISA_F008_S000_I002
p76
sg35
Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception
p77
sg37
VUnprivileged ISA\u000aChapter 8.2
p78
sg39
VOutput result:\u000a\u000aAll bits of rd are toggled
p79
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp80
sg15
(lp81
sg52
(lp82
sg13
(dp83
g55
I0
ssbtp84
a(V003
p85
g1
(g29
g3
Ntp86
Rp87
(dp88
g8
V003
p89
sg23
VVP_ISA_F008_S000_I003
p90
sg35
Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception
p91
sg37
VUnprivileged ISA\u000aChapter 8.2
p92
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exceptio
p93
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp94
sg15
(lp95
sg52
(lp96
sg13
(dp97
g55
I0
ssbtp98
asVrfu_list_1
p99
(lp100
sg52
(lp101
sg13
(dp102
sbtp103
a(V001_SC.W
p104
g1
(g18
g3
Ntp105
Rp106
(dp107
g22
I4
sg8
g104
sg23
VVP_IP008_P001
p108
sg25
(dp109
sg12
I1
sg15
(lp110
(V000
p111
g1
(g29
g3
Ntp112
Rp113
(dp114
g8
V000
p115
sg23
VVP_ISA_F008_S001_I000
p116
sg35
Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1  with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds.
p117
sg37
VUnprivileged ISA\u000aChapter 8.2
p118
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p119
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp120
sg15
(lp121
sg52
(lp122
sg13
(dp123
g55
I0
ssbtp124
a(V001
p125
g1
(g29
g3
Ntp126
Rp127
(dp128
g8
V001
p129
sg23
VVP_ISA_F008_S001_I001
p130
sg35
Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1  with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds.
p131
sg37
VUnprivileged ISA\u000aChapter 8.2
p132
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p133
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp134
sg15
(lp135
sg52
(lp136
sg13
(dp137
g55
I0
ssbtp138
a(V002
p139
g1
(g29
g3
Ntp140
Rp141
(dp142
g8
V002
p143
sg23
VVP_ISA_F008_S001_I002
p144
sg35
Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1  with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds.
p145
sg37
VUnprivileged ISA\u000aChapter 8.2
p146
sg39
VOutput result:\u000a\u000ard is either zero or non-zero to indicate success or failure, respectively
p147
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp148
sg15
(lp149
sg52
(lp150
sg13
(dp151
g55
I0
ssbtp152
a(V003
p153
g1
(g29
g3
Ntp154
Rp155
(dp156
g8
V003
p157
sg23
VVP_ISA_F008_S001_I003
p158
sg35
Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1  with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds.
p159
sg37
VUnprivileged ISA\u000aChapter 8.2
p160
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p161
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp162
sg15
(lp163
sg52
(lp164
sg13
(dp165
g55
I0
ssbtp166
asg99
(lp167
sg52
(lp168
sg13
(dp169
sbtp170
asVrfu_list_0
p171
(lp172
sg99
(lp173
sVvptool_gitrev
p174
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p175
sVio_fmt_gitrev
p176
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p177
sVconfig_gitrev
p178
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p179
sVymlcfg_gitrev
p180
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p181
sbtp182
.